Semiconductor manufactures utilize a wide variety of techniques to improve the performance of semiconductor devices, such as metal oxide semiconductor field effect transistors (MOSFETs). FIG. 1 shows a conventional MOSFET device. The MOSFET of FIG. 1 is fabricated on a semiconductor substrate 10 within an active area bounded by shallow trench isolations 12 that electrically isolate the active area of the MOSFET from other IC components fabricated on the substrate 10.
The MOSFET is comprised of a gate electrode 14 that is separated from a channel region in the substrate 10 by a thin first gate insulator 16 such as silicon oxide or oxide-nitride-oxide (ONO). To minimize the resistance of the gate 14, the gate 14 is typically formed of a doped semiconductor material such as polysilicon.
The source and drain of the MOSFET are provided as deep source and drain regions 18 formed on opposing sides of the gate 14. Source and drain silicides 20 are formed on the source and drain regions 18 and are comprised of a compound comprising the substrate semiconductor material and a metal such as cobalt (Co) or nickel (Ni) to reduce contact resistance to the source and drain regions 18. The source and drain regions 18 are formed deeply enough to extend beyond the depth to which the source and drain silicides 20 are formed. The source and drain regions 18 are implanted subsequent to the formation of a spacer 28 around the gate 14 and gate insulator 16 which serves as an implantation mask to define the lateral position of the source and drain regions 18 relative to the channel region beneath the gate.
The gate 14 likewise has a silicide 24 formed on its upper surface. The gate structure comprising a polysilicon material and an overlying silicide is sometimes referred to as a polycide gate.
The source and drain of the MOSFET further comprise shallow source and drain extensions 26. As dimensions of the MOSFET are reduced, short channel effects resulting from the small distance between the source and drain cause degradation of MOSFET performance. The use of shallow source and drain extensions 26 rather than deep source and drain regions near the ends of the channel helps to reduce short channel effects. The shallow source and drain extensions are implanted prior to the formation of the spacer 22, and the gate 14 acts as an implantation mask to define the lateral position of the shallow source and drain extensions 26 relative to the channel region 18. Diffusion during subsequent annealing causes the source and drain extensions 26 to extend slightly beneath the gate 14.
One option for increasing the performance of MOSFETs is to enhance the carrier mobility of silicon so as to reduce resistance and power consumption and to increase drive current, frequency response and operating speed. A method of enhancing carrier mobility that has become a focus of recent attention is the use of silicon material to which a tensile strain is applied.
“Strained” silicon may be formed by growing a layer of silicon on a silicon germanium substrate. The silicon germanium lattice is generally more widely spaced than a pure silicon lattice as a result of the presence of the larger germanium atoms in the lattice. Because the atoms of the silicon lattice align with the more widely spread silicon germanium lattice, a tensile strain is created in the silicon layer. The silicon atoms are essentially pulled apart from one another. The amount of tensile strain applied to the silicon lattice increases with the proportion of germanium in the silicon germanium lattice.
Relaxed silicon has six equal valence bands. The application of tensile strain to the silicon lattice causes four of the valence bands to increase in energy and two of the valence bands to decrease in energy. As a result of quantum effects, electrons effectively weigh 30 percent less when passing through the lower energy bands. Thus the lower energy bands offer less resistance to electron flow. In addition, electrons encounter less vibrational energy from the nucleus of the silicon atom, which causes them to scatter at a rate of 500 to 1000 times less than in relaxed silicon. As a result, carrier mobility is dramatically increased in strained silicon as compared to relaxed silicon, offering a potential increase in mobility of 80% or more for electrons and 20% or more for holes. The increase in mobility has been found to persist for current fields of up to 1.5 megavolts/centimeter. These factors are believed to enable a device speed increase of 35% without further reduction of device size, or a 25% reduction in power consumption without a reduction in performance.
An example of a MOSFET using a strained silicon layer is shown in FIG. 2. The MOSFET is fabricated on a substrate comprising a silicon germanium layer 30 on which is formed an epitaxial layer of strained silicon 32. The MOSFET uses conventional MOSFET structures including deep source and drain regions 18, shallow source and drain extensions 26, a gate oxide layer 16, a gate 14 surrounded by spacers 28, 22, silicide source and drain contacts 20, a silicide gate contact 24, and shallow trench isolations 12. The channel region of the MOSFET includes the strained silicon material, which provides enhanced carrier mobility between the source and drain.
One detrimental property of strained silicon MOSFETs of the type shown in FIG. 2 is that the band gap of silicon germanium is lower than that of silicon. In other words, the amount of energy required to move an electron into the conduction band is lower on average in a silicon germanium lattice than in a silicon lattice. As a result, the junction leakage in devices having their source and drain regions formed in silicon germanium is greater than in comparable devices having their source and drain regions formed in silicon.
Another detrimental property of strained silicon MOSFETs of the type shown in FIG. 2 is that the dielectric constant of silicon germanium is higher than that of silicon. As a result, MOSFETs incorporating silicon germanium exhibit higher parasitic capacitance, which increases device power consumption and decreases driving current and frequency response.
Therefore, the advantages achieved by incorporating strained silicon into MOSFET designs are partly offset by the disadvantages resulting from the use of a silicon germanium substrate.
Thus, there is a need for a MOSFET fabrication process in which silicon is strained by the highly compressive deposition of layers on top of the silicon. Further, there is a need to increase tensile strain in a silicon MOSFET without changing a silicon germanium layer. Even further, there is a need to increase carrier mobility using strained silicon.